The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Some network devices, such as network switches, routers, edge devices and the like employ parallel packet processing in which multiple programmable packet processing elements simultaneously and in parallel perform various processing operations on different packets. In other network devices, a pipeline architecture employs sequentially arranged programmable packet processing elements such that different packet processing elements in the pipeline may be processing different packets at a given time. In some such systems, the processing elements engage various external resources, such as hardware accelerators, for performing certain processing operations on the packets. In such systems, it is important to efficiently utilize the respective packet processing elements and to minimize latency when processing packets by the network devices. One type of operation that a network device needs to efficiently perform is the generation of one or more lookup keys, based on information in a packet, that are subsequently utilized when performing various packet processing operations on the packet.